1. Field of the Invention
The present invention relates to a code translation circuit for converting a binary data, which is used for displaying an operation result and so on, to a binary coded decimal data Hereinafter, in this specification, "binary" data and "binary coded decimal" data are referred to as "BIN" data and "BCD" data, respectively.
2. Prior Art
Conventionally, a digital operation is processed in a BIN data format, and then the resultant is converted to a BCD data for display, because of that the BCD data is clearly in aid of human recognition. Accordingly, various code translation circuits for converting BIN data to BCD data have been developed.
Such a code translation circuit usually performs a translation process for each bit of the BIN data. For example, for converting (n+1) bits BIN data b.sub.n . . . b.sub.1 b.sub.0 to a BCD data, plural calculations with decimal correction are sequentially performed for each parenthesized term in the following expression (1). EQU D=b.sub.n .times.2.sup.n +b.sub.n-1 .times.2.sup.n-1 + . . . +b.sub.2 .times.2.sup.2 +b.sub.1 .times.2.sup.1 +b.sub.o =((. . . (b.sub.n .times.2+b.sub.n-1).times.2+ . . . ).times.2+b.sub.1).times.2+b.sub.o. . .(1)
For example, when each 4 bits of a BCD data is parenthesized, the decimal correction may be performed as follows. When a carry signal is generated in each 4 bits data or each 4 bits data is over 10 as a result of operation for each parenthesized terms in the above BIN data, the decimal correction is performed in such a manner that .left brkt-top.0111(6).right brkt-bot. is added to the 4 bits data. In the expression of .left brkt-top.0110(6).right brkt-bot., the perenthesized number 6 is expressed by a hexadecimal number system or a decimal system. Hereinafter, similar expressions will be used.
In details, when a BIN data .left brkt-top.1000 1101 (8D).right brkt-bot. is converted to a BCD data .left brkt-top.0001 0100 0001(141).right brkt-bot., the following sequential operations are performed as shown in the following table 1.
TABLE 1 ______________________________________ 1 0 .times. 2 + b.sub.7 (1) .fwdarw. 0000 0000 0001 2 1 .times. 2 + b.sub.6 (0) .fwdarw. 0000 0000 0010 3 2 .times. 2 + b.sub.5 (0) .fwdarw. 0000 0000 0100 4 3 .times. 2 + b.sub.4 (0) .fwdarw. 0000 0000 1000 5 4 .times. 2 + b.sub.3 (1) .fwdarw. 0000 1 #STR1## 0001 (carry generation) +) 0110 (decimal correction) 0000 0001 0111 6 5 .times. 2 + b.sub.2 (1) .fwdarw. 0000 0010 2 #STR2## (.gtoreq.10) +) 0110 (decimal correction) 0000 0011 0101 7 6 .times. 2 + b.sub.1 (0) .fwdarw. 0000 0110 3 #STR3## (.gtoreq.10) +) 0110 (decimal correction) 0000 0111 0000 8 7 .times. 2 + b.sub.0 (1) .fwdarw. 0000 4 #STR4## 0001 (.gtoreq.10) +) 0110 (decimal correction) RESULT .fwdarw. 0001 0100 0001 (141) ______________________________________
As described above, although the converting procedure is simple in the conventional BIN-to-BCD converter, it is necessary to perform (n+1) operations for (n+1) bits BIN data. Therefore, operation time is long, and power consumption is large because of that many shift operations must be performed in a shift-register. The fact of that operation time is long brings a high operation frequency, whereby the power consumption of, for example, oscillator and the like, becomes large.